1 ltc1329-10/ ltc1329-50/ltc1329a-50 micropower 8-bit current output d/a converter n guaranteed precision full-scale dac output current at 25 c: ltc1329a-50 50 m a 1% ltc1329-10 10 m a 3% ltc1329-50 50 m a 3% n wide output voltage dc compliance: C 15v to 2.5v n wide supply range: 2.7v v cc 6.5v n supply current in shutdown: 0.2 m a n low supply current: 75 m a for ltc1329-10, 95 m a for ltc1329-50/ltc1329a-50 n available in 8-pin so n triple mode tm interface modes 1. standard 3-wire mode 2. pulse mode 1-wire interface: increment-only 3. pulse mode 2-wire interface: increment/decrement n can read back the 8-bit dac value in 3-wire mode n dac powers up at midrange n dac contents are retained in shutdown features descriptio n u applicatio n s u n lcd contrast control n backlight brightness control n battery charger current/voltage adjustment n power supply voltage adjustment n trimmer pot elimination typical applicatio n u digitally controlled lcd bias generator 1
2 8
7 d out
d in i out
v cc
shdn
clk ltc1329-50 gnd
cs 47 m f 1329 ta01 v out
22v at 40ma v in
5v 200k 3
4 6
5 4.7 m f 22 m f 0.1 m f lt 1173 1n4148 1n5818 1n5818 l1*
100 m h *gowanda ga10-103k or
coiltronics ctx100-4 i lim v in fb sw2 gnd sw1 220k 47 w 10.1k mpu
(e.g., 8051) p1.2
p1.1
p1.0 + + + the ltc ? 1329-10/ltc1329-50/ltc1329a-50 are micropower 8-bit current output d/a converters (dacs) with an output range of 0 m a to 10 m a for the ltc1329-10 and 0 m a to 50 m a for the ltc1329-50/ltc1329a-50. the dac current output can be biased from C 15v to 2v or C 15v to 2.5v in 3.3v and 5v systems, respectively. supply current is only 95 m a for the ltc1329-50/ltc1329a-50 and 75 m a for ltc1329-10. a shutdown mode drops the supply current to 0.2 m a. the ltc1329 can communicate with external circuitry by using one of three interface modes: standard 3-wire serial mode and two pulse modes. upon power-up, the internal counter resets to 1000 0000b, the dac output assumes midrange and the chip is configured in 3-wire or pulse mode depending on the signal level at cs. in 3-wire mode, the system mpu can serially transfer 8-bit data to and from the ltc1329. in pulse mode, the upper six bits of the dac output can be programmed for incre- ment-only (1-wire interface) or increment/decrement (2-wire interface) operation depending on the signal level at d in . ltc1329 is available in 8-pin so packages. , ltc and lt are registered trademarks of linear technology corporation. triple mode is a trademark of linear technology corporation.
2 ltc1329-10/ ltc1329-50/ltc1329a-50 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u (note 1) supply voltage (v cc ) ................................................ 7v input voltage (all inputs)............ C 0.3v to (v cc + 0.3v) output voltage i out ......................................... C 15v to (v cc + 0.3v) d out ....................................... C 0.3v to (v cc + 0.3v) short-circuit duration (all outputs) ............... indefinite operating temperature range .................... 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc1329cs8-10 ltc1329cs8-50 ltc1329acs8-50 t jmax = 125 c, q ja = 150 c/ w s8 part marking 1329a5 13291 13295 consult factory for industrial and military grade parts. v cc = 3.3v, t a = 25 c, unless otherwise specified. ltc1329-10 ltc1329-50/ltc1329a-50 symbol parameter conditions min typ max min typ max units v cc l 2.7 6.5 2.7 6.5 v i cc supply current v shdn = v din = v cs = v cc , v clk = 0v, l 75 130 95 150 m a d out = nc, i out = nc shutdown l 0.2 5 0.2 5 m a dac resolution 8 8 bits dac full-scale current output voltage at i out = 0.45v, t a = 25 c 9.7 10 10.3 48.5 50 51.5 m a (ltc1329-10, ltc1329-50) l 9.5 10 10.5 47.5 50 52.5 m a output voltage at i out = 0.45v, t a = 25 c 49.5 50 50.5 m a (ltc1329a-50) l 49.0 50 51.0 m a dac zero-scale current output voltage at i out = 0.45v l 200 200 na dac differential monotonicity guaranteed l 0.3 0.9 0.9 lsb nonlinearity supply voltage rejection v cc = 3v to 5.5v, i out = full scale, l 1 2 1 2 lsb output voltage at i out = 0.45v v cc = 2.7v to 6.5v, full scale, l 2.5 4 2.5 4 lsb output voltage at i out = 0.45v output voltage rejection v cc = 5v, i out = full scale, l 0.25 1 0.25 lsb output voltage at i out = C 15v to 0v v cc = 5v, i out = full scale, l 1.5 1.5 lsb output voltage at i out = 0v to 2.5v i ih , i il logic input current 0v v in v cc l 1 1 m a v ih high level input voltage v cc = 5v l 2.0 2.0 v v cc = 3.3v l 1.9 1.9 v v il low level input voltage v cc = 5v l 0.80 0.80 v v cc = 3.3v l 0.45 0.45 v v oh high level output voltage v cc = 5v, i o = 400 m a l 2.4 2.4 v v cc = 3.3v, i o = 400 m a l 2.1 2.1 v v ol low level output voltage v cc = 5v, i o = 2ma l 0.4 0.4 v v cc = 3.3v, i o = 1ma l 0.4 0.4 v i oz three-state output leakage v cs = v cc l 5 5 m a electrical characteristics 1
2
3
4 8
7
6
5 top view d out
d in (up/dn)
gnd
cs i out
v cc
shdn
clk s8 package
8-lead plastic so
3 ltc1329-10/ ltc1329-50/ltc1329a-50 v cc = 3.3v, unless otherwise specified. (notes 2, 3) reco e ded operati g co ditio s u u u uw w symbol parameter conditions min typ max units serial interface f clk clock frequency l 2 mhz t cks setup time, clk before cs l 150 ns t css setup time, cs before clk - l 400 ns t dv cs to d out valid see test circuits l 150 ns t ds d in setup time before clk - l 150 ns t dh d in hold time after clk - l 150 ns t do clk to d out valid see test circuits l 150 ns t ckhi clk high time l 200 ns t cklo clk low time l 250 ns t csh clk before cs - l 150 ns t dz cs - to d out in hi-z see test circuits l 400 ns t ckh cs - before clk - l 400 ns t cslo cs low time f clk = 2mhz (note 4) l 4550 ns v clk = 0v l 400 ns t cshi cs high time l 400 ns note 2: timing for all input signals is measured at 0.8v for a high-to-low transition and at 2v for a low-to-high transition. note 3: timing specification are guaranteed but not tested. note 4: this is the minimum time required for valid data transfer. the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. typical perfor m a n ce characteristics u w code 0 dnl (lsb) 1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0 64 128 160 1392 g01 32 96 192 224 256 t a = 25 c
v cc = 3.3v
v(i out ) = 0.45v code 0 inl (lsb) 1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0 64 128 160 1329 ?tpc02 32 96 192 224 256 t a = 25 c
v cc = 3.3v
v(i out ) = 0.45v code 0 dnl (lsb) 1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0 64 128 160 1392 g03 32 96 192 224 256 t a = 25 c
v cc = 3.3v
v(i out ) = 0.45v ltc1329-10 dnl vs code ltc1329-10 inl vs code ltc1329-50 dnl vs code
4 ltc1329-10/ ltc1329-50/ltc1329a-50 typical perfor m a n ce characteristics u w temperature ( c) 0 full-scale i out error (lsb) 3
2
1
0
?
?
? 30 50 1329 g05 10 20 40 60 70 v cc = 3.3v
v(i out ) = 0.45v ltc1329-50 ltc1329-10 code 0 inl (lsb) 1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0 64 128 160 1329 ?tpc04 32 96 192 224 256 t a = 25 c
v cc = 3.3v
v(i out ) = 0.45v ltc1329-10/ltc1329-50 full- scale current vs temperature supply voltage (v) 0 full-scale i out error (lsb) 2
1
0
?
? 35 1329 g06 12 467 t a = 25 c
v(i out ) = 0.45v ltc1329-50 ltc1329-10 ltc1329-10/ltc1329-50 supply voltage rejection ltc1329-50 inl vs code pi n fu n ctio n s uuu i out (pin 1): dac current output. in 3.3v or 5v systems, the dac current output can be biased from C 15v to 2v or C 15v to 2.5v respectively. v cc (pin 2): voltage supply (2.7v v cc 6.5v). this supply must be kept free from noise and ripple by bypass- ing directly to the ground plane. shdn (pin 3): shutdown. a logic low puts the chip into shutdown mode. the digital setting for the dac is retained. clk (pin 4): shift clock. this clock synchronizes the serial data in 3-wire mode. this pin has a schmitt trigger input. cs (pin 5): chip select input. in 3-wire mode, a logic low on this cs pin enables the ltc1329. upon power-up, a logic high at cs puts the chip into pulse mode. if cs ever goes low, the chip is configured in 3-wire mode until the next power is cycled. gnd (pin 6): ground. ground should be tied directly to a ground plane. d in (up/dn)(pin 7): data input. in 3-wire mode, the dac data is shifted into d in on the rising edge of clk. in pulse mode, upon power-up a logic high at d in puts the counter into increment-only mode. if d in ever goes low, the i out bias voltage (v) ?5 full-scale i out error (lsb) 0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5 ? 0 1329 g07 ?2 9 ? 3 6 t a = 25 c
v cc = 3.3v ltc1329-50 ltc1329-10 ltc1329-10/ltc1329-50 bias voltage rejection (full-scale current) i out bias voltage (v) ?5 zero-scale i out current (na) 50
40
30
20
10
0
10
20
30
40
?0 ? 0 1329 g08 ?2 9 ? 3 6 ltc1329-10 ltc1329-50 ltc1329-10/ltc1329-50 bias voltage rejection (zero-scale current) supply voltage (v) 2.7 maximum i out bias voltage (v) 6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5 3.7 4.7 5.2 1329 ?tpc09 3.2 4.2 5.7 6.2 6.7 t a = 25 c
i out = full-scale current maximum i out bias voltage vs supply voltage
5 ltc1329-10/ ltc1329-50/ltc1329a-50 pi n fu n ctio n s uuu counter is configured in increment/decrement mode until the power is cycled. d out (pin 8): data output. in 3-wire mode, on every conversion d out serially outputs the previous 8-bit dac data. in pulse mode, d out is three-stated. block diagra w latch
and
logic latch
and
logic 8-bit
current
dac clk shdn clk 1329 bd d in d out up/dn 8-bit dac register/counter i out v cc d out 8 8 8 9-bit shift register voltage
reference up only/
up/dn mode select
0 = pulse
1 = 3-wire power-on
reset control
logic clk
d in (up/dn)
cs
shdn shdn test circuits
voltage waveforms for t do 0.8v 0.4v 2.4v 1329 tc03 d out clk t do voltage waveforms for t dz , t dv 1329 tc04 0.8v cs d out
set high d out
set low 2.4v 2.0v 90% 10% 0.4v t dv t dz hi-z hi-z hi-z hi-z 3k 100pf 1329 tc01 1.4v d out 3k 100pf 1329 tc02 5v t dz waveform 2, t dv t dz waveform 1 d out load circuit for t do load circuit for t dz, t dv
6 ltc1329-10/ ltc1329-50/ltc1329a-50 serial i/o operati g seque ce
u
u
figure 1. 3-wire interface timing specification d in clk cs d7 d6 d5 d4 d3 d2 d1 d0 hi-z d7 d6 d5 d4 d3 d2 d1 d0 d7 t dz hi-z 1329 f01 d out t do t ckhi t dh t ds t css t cks t cslo t dv t cklo t csh t cshi t ckh applicatio n s i n for m atio n wu u u 8-bit current output dac the ltc1329-10/ltc1329-50/ltc1329a-50 are 8-bit, current output digital-to-analog (dac) converters. for each part, the 8-bit dac output is guaranteed monotonic and is digitally adjustable in 256 equal steps. upon power up, the internal dac register resets to 10000000b and the dac output assumes midrange. the current output (i out ) can be biased from C 15v to 2v or C 15v to 2.5v in 3.3v and 5v systems, respectively. the ltc1329-10 features a full- scale output of 10 m a trimmed to 3% at room tempera- ture ( 5% over temperature), while the ltc1329-50 features a 50 m a full scale and two accuracy grades; 1% at room temperature ( 2% over temperature) for the ltc1329a-50 and 3% at room temperature ( 5% over temperature) for the ltc1329-50. all versions include a flexible serial digital interface which allows easy intercon- nection to a variety of digital systems. digital interface automatic mode selection the ltc1329 family includes a serial interface capable of communicating with the host system using one of three protocols; standard 3-wire mode, a 2-wire up/down pulse mode and a 1-wire increment-only pulse mode. the ltc1329 family is designed to auto-configure itself de- pending on the way data is presented to it. a diagram illustrating this auto detection behavior is shown in figure 2. at power-up, the interface is set to 1-wire pulse mode. if the cs line ever goes low (as it will at the beginning of a valid 3-wire serial transfer) the chip immediately reconfigures itself into 3-wire mode and remains in this mode until the next time the power is cycled. if cs stays high, the ltc1329 family stays in pulse mode and watches the up/dn pin to determine whether to switch to 2-wire mode. if up/dn ever goes low (as it will the first time a down command is given) the chip switches into 2-wire pulse mode and remains in this mode until the next time the power is cycled. in a properly configured 1-wire system, cs and up/dn will stay high continuously and the ltc1329-10/ltc1329-50/ltc1329a-50 will remain in 1- wire pulse mode. 2-wire pulse mode systems should give a single down pulse sometime before the first data pulses are sent to prevent the ltc1329 family from staying in 1-wire mode if the first several pulses happen to be ups. power-up 3-wire mode pulse mode 1329 f02 increment/
decrement increment-
only cs stays
high cs goes
low d in (up/dn)
goes low d in stays
high figure 2. ltc1329 operating modes
7 ltc1329-10/ ltc1329-50/ltc1329a-50 applicatio n s i n for m atio n wu u u standard 3-wire mode (figure 3) refer to the serial interface operating sequence in figure 1. when operating in 3-wire mode, the ltc1329-10/ ltc1329-50/ltc1329a-50 will interface directly with most standard 3- or 4-wire serial interface systems. the clock (clk) input synchronizes the data transfer with each input bit captured at the rising edge of clk and each output data bit shifted out through d out at the falling edge. a falling edge at cs initiates the data transfer and brings the d out pin out of three-state. the serial 8-bit data representing the new dac setting is shifted into the d in pin. simulta- neously, the previous dac setting is shifted out of the d out pin. after the new data is shifted in, a rising edge at cs transfers the data from the input shift register into the dac register. the dac output assumes the new value and the d out pin returns to a high-impedance state. i out = (b7 b6 b5 b4 b3 b2 b1 b0)i fullscale /255 1
2 shdn clk cs d in d out 8
7 d out
d in i out
v cc
shdn
clk ltc1329 gnd
cs 1329 f03 i out 3
4 6
5 v cc 0.1 m f d in and d out can be tied together
for half duplex data transfer figure 3. 3-wire mode; serial interface (3-wire control by cs, clk and d in ) 1-wire interface (pulse mode, figure 4) in 1-wire pulse mode, each rising edge at clk increments the upper six bits of the dac register by one count. when incramented beyond 11111100b, the counter rolls over and sets the dac to the minimum value (00000000b). in this way, a single pulse applied to clk increases the dac output by a single 4-lsb step and 63 pulses decrease the dac output by one step. the last two lsbs are always zero in pulse mode. i out = (b7 b6 b5 b4 b3 b2 0 0)i fullscale /255 to configure the ltc1329-10/ltc1329-50/ltc1329a-50 in 1-wire pulse mode, tie both the cs and d in pins to v cc . 1
2 shdn clk 8
7 d out
d in i out
v cc
v cc
shdn
clk ltc1329 gnd
cs 1329 f04 i out 3
4 6
5 0.1 m f figure 4. pulse mode: increment only (1-wire control by clk) 2-wire interface (pulse mode, figure 5) in 2-wire pulse mode, a logic high at up/dn programs the dac register to increment and each rising edge at clk increments the upper six bits of the register by one count. similarly, a logic low at up/dn set the dac register to decrement and a rising edge at clk decrements the upper six bits of the register by one count. each count in 2-wire mode changes the dac output by a single four lsb step. the dac register stops incramenting at 11111100b and stops decrementing at 00000000b and will not roll over in 2-wire pulse mode. the last two lsbs are always zero in pulse mode. i out = (b7 b6 b5 b4 b3 b2 0 0)i fullscale /255 to configure the ltc1329-10/ltc1329-50/ltc1329a-50 in 2-wire pulse mode, tie cs to v cc and bring the up/dn pin low at least once during power-up. 1
2 shdn clk up/dn 8
7 d out
d in i out
v cc
v cc
shdn
clk ltc1329 gnd
cs 1329 ta04 i out 3
4 6
5 0.1 m f figure 5. pulse mode; increment/decrement (2-wire control by clk and up/dn) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
8 ltc1329-10/ ltc1329-50/ltc1329a-50 1329f lt/tp 0297 5k ? printed in usa ? linear technology corporation 1997 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com digitally controlled power supply adjustment 1
2 8
7 d out
d in i out
v cc
shdn
clk ltc1329-50 gnd
cs 47 m f 1329 ta03 v out
5v (150ma) to
30v (14ma) v in
3v 510k 3
4 6
5 100 m f lt1107 1n5817 l1*
33 m h *coiltronics ctx33-4 i lim v in fb sw2 gnd sw1 47 w 22k mpu
(e.g., 8051) p1.2
p1.1
p1.0 + + part number description comments ltc1451 12-bit micropower serial input v out dac higher resolution, 8-pin so ltc1452 12-bit multiplying serial input v out dac higher resolution, 8-pin so ltc8043 12-bit multiplying serial input i out dac higher resolution, 8-pin so related parts u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) pulse mode: increment-only (1-wire control by clk) with voltage output 1
2 shdn clk v bias r fb
100k 8
7 d out
d in i out
v cc
shdn
clk ltc1329 v cc v ee 6 7 2 3 4 gnd
cs 1329 ta02 v out v out = ( i out )(r fb + v bias )
v ee < v bias + v out
3
4 6
5 + lt1006 0.1 m f for v cc = 3.3v, ?5v v bias 2v
for v cc = 5v, ?5v v bias 2.5v typical applicatio n s u 1 2 3 4 0.150 ?0.157**
(3.810 ?3.988) 8 7 6 5 0.189 ?0.197*
(4.801 ?5.004) 0.228 ?0.244
(5.791 ?6.197) 0.016 ?0.050
0.406 ?1.270 0.010 ?0.020
(0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010
(0.203 ?0.254) so8 0996 0.053 ?0.069
(1.346 ?1.752) 0.014 ?0.019
(0.355 ?0.483) 0.004 ?0.010
(0.101 ?0.254) 0.050
(1.270)
typ dimension does not include mold flash. mold flash
shall not exceed 0.006" (0.152mm) per side
dimension does not include interlead flash. interlead
flash shall not exceed 0.010" (0.254mm) per side
*
**
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